Edaptive Computing, Inc.
1245-G Lyons Road
Dayton, OH 45458
Junior Computer/FPGA Engineer
This opportunity is to become a member of the Edaptive Computing Development Team. The Junior Computer/FPGA Engineer will participate in projects that involve both software as well as hardware. The work will encompass all design lifecycle sub-processes, including: specification, design, implementation, and testing.
Developer will model, simulate, and analyze complex systems and processes, including: research and implementation of advanced concepts, technologies, products, processes, and/or methods.
Full time with competitive benefits package
BS/MSEE, BS/MSCE, BS/MSECE
New Graduate, 1-5 years experience recommended
Required Skills and Abilities:
Knowledge of computer architecture and Operating Systems
Familiarity with VHDL or Verilog
Familiarity with Altera, Xilinx, or Actel FPGAs
Design verification with the use of modeling and simulation tools such as Modelsim or ActiveHDL
Desired Skills and Abilities:
Coursework/Experience in Digital Systems design
Coursework/Experience in Computer Architecture and Operating Systems
Coursework/Experience in Programming
Enhancing Skills and Abilities:
Active U.S. Security Clearance
Submission Instructions (Non-complying submissions will not be considered):
Reference Junior Computer/FPGA Engineer in all correspondence
Eligibility for a Security Clearance is required
Resumes must be 3 pages or less and provide description of how qualifying technologies were used. You may also submit a one page cover letter (optional but desired) stating your career objectives and how your qualifications and interest align with our requirements.
You must complete the applicant profile by clicking Apply Here at the bottom of the page. The process for submitting all information is not complete until you hit the submit button.